The present invention relates to a digital demodulating circuit and method of a time-division multiple access (TDMA) channel for use in radio communications, and more particularly to a circuit and method for demodulating a .pi./4-DQPSK (differentially quadrature phase shift keying) modulated signal.
Generally, .pi./4-DQPSK is one of digital modulation systems for modulating the phase of a transmission signal. The .pi./4-DQPSK demodulation has an advantage in that band diffusion caused by the instantaneous phase transition of a modulated signal is small since it has maximum instantaneous transition value smaller than that of a traditional QPSK modulation system.
An example of a conventional .pi./4-DQPSK demodulator is shown in FIG. 1. A .pi./4-DQPSK modulated signal is received to a linear receiver 103 through an antenna 101. The output of the linear receiver 103 is applied to a delay circuit 125 and to a frequency multiplier 105. The 4 frequency multiplied output through the frequency multiplier 105 and the output of a 1/2 symbol clock circuit 109 are mixed in a mixer 107 to detect an accurate data clock at a base band of a received signal band from the output of the frequency multiplier 105. The output of the mixer 107 is filtered with a constant band through a band-pass filter 111 and then applied to a limiter 113. The limiter 113 eliminates a part beyond a given range among input signals and the output thereof is 4-frequency demultiplied in a frequency demultiplier 115. The output of the frequency demultiplier 115 is applied to a multiplier 119 and to a phase shifter 117. The phase shifter 117 phase-shifts the output of the demultiplier 115 by 90.degree. and the phase-shifted output is supplied to a multiplier 121. Meanwhile, the delay circuit 125 delays the output of the linear receiver 103 and applies the delayed output to the multipliers 119 and 121. The multipliers 119 and 121 multiply the delayed signal through the delay circuit 125 by the output of the demultiplier 115 and the output of the phase shifter 117, respectively. A differential phase detector 123 receiving the outputs of the multipliers 119 and 121 generates binary data in accordance with the phase difference between the outputs of the multipliers 119 and 121.
However, such as a demodulated method should use a phase synchronizing loop circuit including a symbol clock recovery circuit, or a frequency multiplier of second order or more, etc. in order to accurately detect binary data. Therefore, the design is very complicate and circuit construction for a desired function is difficult.